Design and Analysis of RCA and CLA using CMOS, GDI, TG and ECRL Technology

VLSI technology has developed over the years thereby enhancing the performance of chips in terms of three basic constraints viz. delay, power and area. In today's scenario compact and small digital devices are critical concern in the field of VLSI design, which should perform fast as well as low power consumption. Optimizing the delay, area and power of an adder is a major design issues, as area and speed are usually conflicting constraints. Adders can be designed with conventional CMOS technology but for compact and low power consumption we can design circuit using adiabatic logic and with other technology GDI,ECRL, transmission Gate.


I. INTRODUCTION
Full adders can be designed using multiple techniques out of which Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) are considered for comparison based on their power and speed. In the designing of the digital circuits speed and power is conflict to each other. A Ripple Carry Adder consumes the least power but is the slowest (propagation delay is the most) while Carry Look-ahead Adder is the fastest but requires more power.

II. BASIC ADDER BLOCKS 2.1 HALF ADDER
The circuit is created using the combination of an XOR and an AND Gate. Each gate handles a component of the output. The AND Gate takes the input and give the carry bit and the XOR gate outputs the sum bit. A and B are the inputs and SUM and CARRY are the output signals Boolean equations for a half adder is given below:

Full Adder
A Full adder is an extension of the half adder. This works by taking the carry bit from previous addition and using this along with the two input operand bits. This means that this adder can be used to add binary numbers with more than 1 bit. It functions by taking into account the two input bits as well as the carry bit, passing them through a set of gates and giving a sum and carry bit as the output [2]. Boolean equations for a full adder are given below:

Multiple Bit Adders
 Ripple-Carry Adder: A Ripple carry adder is designed using cascading connections of multiple full adders. What this means is that the carry out signal of the preceding full adder is the carry in signal for the succeeding full adder and so on. Ripple-Carry adder is the most compact adder (O (n) Area) among all the adders. This adder can be used to design compact devices on the cost of speed as this adder is very slow (O (n) time) for computation. In case of fast addition, carry increment and carry skip architecture can be used, particularly for 8 to 16 bit lengths.  Carry-Look ahead Adder: Carry-Look ahead adders (CLA) are the fastest adders, but they consume maximum area and little bit complex. This adder is preferred for addition up to 4 bit length.   .org/10.22161/ijaers.4.11.19  ISSN: 2349-6495(P) | 2456-1908(O) adder "ripples" to the next.An RCA uses lesser number of transistors thus reducing the power dissipation.The input signals to an 8-bit adder are: a0-a7, b0-b7 and cin and sum0-sum7 & cout are the output signals.

Implementation of a Carry Look-Ahead Adder
CLAs utilize the concept of the generate (g), kill (k) and the propagate (p) signals. These generate and propagate signals are represented as: where, ai and bi are the input signals. The carry signal, Cin, and the sum signal, Si, are given by: These sum and carry signals are generated using these main componentsan XOR gate, an AND gate and a gi+pi.ci Boolean expression logic circuit. In the following sections, working of the above mentioned components are explained for 4 different techniques -Conventional CMOS, Transmission Gate, Gate Diffusion Input and ECRL [3].
 8-Bit CLA Using Conventional CMOS To design N-bit adder, N 1-bit adders are required. In the case of Carry Look-ahead adders, these 1-bit adders are designed using 2 XOR gates, 1 AND gate and a gi+pi.ci boolean expression logic circuit. Here, for a 1-bit adder, 19-PMOS and 19-NMOS transistors are required.
 8-Bit CLA Using Transmission Gate (TG) For designing a 1-bit adder based on TG logic , the circuit components used are -2 XOR gates and a boolean expression logic, gi + pi.ci, circuit. The design of these circuit components is different from the way it is done in Conventional CMOS design. 1 TG based full adder has 11 PMOS and 11 NMOS transistors.
 8-Bit CLA Using Gate Diffusion Input (GDI) Logic To reduce the power consumption as well as the transistor count further, another technique for creating a full adder is used, called Gate Diffusion Input (GDI). For designing a 1-bit full adder using GDI logic, only 5 PMOS and 5 NMOS transistors are required.
 8-Bit CLA Using ECRL Adiabatic Logic To design a 1-bit adder using ECRL, 2 XOR gates, 1 AND gate and a (gi + pi.ci) boolean expression logic circuit are used. It comprises of 11 NMOS and 25 PMOS transistors which is greater than that required in an RCA [4].

Comparative
Analysis of 8-Bit RCA and CLA By analysing 8bit RCA and CLA for different logic design for different input voltages and frequency we can see that RCA is better in terms of power consumption but delay is very high. Due to this reason, a CLA is used. To reduce the drawback of CLA power consumption we have used adiabatic logic in this work so power level decreases as in RCA circuit CONCLUSION When we compare Ripple Carry Adder and Carry look ahead Adder, CLA is better compare to RCA.CLA is better from RCA using ECRL adiabatic logic in which delay is reduced. And transistor count is also equal for both the logic circuits.