For Authors

Articles & Indexing

Downloads

Statistics

    Map

Twitter

Design and Analysis of 8x8 Wallace Tree Multiplier using GDI and CMOS Technology
( Vol-4,Issue-7,July 2017 )
Author(s):

Pradeep Kumar Kumawat, Gajendra Sujediya

Keywords:

Multiplier, GDI ,CMOS, Wallace tree.

Abstract:

Multiplier is a small unit of an arithmetic circuit that is widely used in Digital filters, Digital Signal Processing, microprocessors and communication applications etc. In today’s scenario compact and small digital devices are critical concern in the field of VLSI design, which should perform fast as well as low power consumption. Optimizing the delay, area and power of a multiplier is a major design issues, as area and speed are usually conflicting constraints. A Wallace tree multiplier is an improved version of tree base multiplier. The main aim of this paper is a reconfigurable 8x8 Wallace Tree multiplier using CMOS and GDI technology. This is efficient in power and regularity without increase in delay and area. The generation of partial products in parallel using AND gates. The addition of partial products is reducing using Wallace Tree which is divided into levels. Therefore there will be a certain reduction in the power consumption, since power is provided only to the level that is involved in computation and the remaining two levels remain off.

ijaers doi crossref DOI:

10.22161/ijaers.4.7.3

Paper Statistics:
  • Total View : 176
  • Downloads : 27
  • Page No: 020-024
Cite this Article:
Show All (MLA | APA | Chicago | Harvard | IEEE | Bibtex)
Share:
Share
References:

[1] P.V. Rao, C. P. R. Prasanna, and S. Ravi, VLSI Design and Analysis of Multipliers for Low Power, IEEE Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Kyoto,2009,pp.1354-1357.
[2] C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Computers, 13, 1964, pp.14-17
[3] Ron S. Waters and Earl E. Swartzlander, “A reduced Comlexity Wallace Multiplier Reduction. IEEE Transactions On Computersl, Vol. 59, No. 8,August 2010.Published by the IEEE computer Society.
[4] Puneet Bhardwaj Dhammi, “Analysis and Implementation of various Adders and Multipliers with Power and Performance Perspectives”, Thapper University Patiala.
[5] K. G. Krishna, B. Santhosh, and V. Sridhar, ”Design of Wallace Tree Multiplier using Compressors”, International Journal of Engineering Sciences & Research Technology, 2, 2013,pp. 2249 - 2254.