Design of High Performance and Energy Efficient Explicit Pulsed Sense Amplifier Based Flip-Flop

Priyanka Sharma

Explicit pulsed SAFF, GDI Technique, latch topology, low power, delay, Power consumption, Dual edge triggered flip flops, sense-amplifier, Tanner EDA.

In this paper, we have presented a new design of explicit pulsed sense amplifier based flip-flop (SAFF) which gives high performance parameters. The most important factors need to be considered while designing efficient circuits are low power with less delay .Our proposed design attracted these performance parameters due to its design using GDI technique. Different topologies along with their layout simulations have been compared with respect to power consumption, delay and temperature sustainability in order to prove the superiority of proposed design. The simulation has been carried out on Tanner EDA tool on BSIM3v3 45nm technology.

10.22161/ijaers.4.4.22