Design of Low Power and Area Efficient Carry Select Adder (CSLA) using Verilog Language

Guguloth Sreekanth, Kethavath Jail Singh, Neelapala Sai Sruthi

Ripple carry adder (RCA), Carry select adder(CSLA), Logic gates, Verilog, Adders.

Carry select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However conventional carry select adder (CSLA) is still area consuming due to the dual ripple carry adder structure. The excessive area overhead makes conventional carry select adder (CSLA) relatively unattractive but this has been the circumvented by the use of add-one circuit. In this an area efficient modified CSLA scheme based on a new first zero detection logic is proposed. The gate count in 32-bit modified CSLA can be greatly reduced, design proposed in this paper has been developed using VERILOG language and synthesized in XILINX13.2 version.

10.22161/ijaers/3.12.16