Implementation of DWT Integrated Log Based FPU with SPIHT Coders on FPGA

N.RamyaRani

Discrete Wavelet Transform, Log based IEEE FPU, SPHIT Algorithm, Block-based pass parallel SPHIT BPS Algorithm, FPGA, Verilog HDL.

In this work, architecture is designed for integrating lifting based discrete wavelet transform (DWT) structure with logarithmic based floating point arithmetic units. As many algorithms were proposed for coding wavelet coefficients for image compression, Set-Partitioning in hierarchical trees algorithm (SPIHT) is found to be widely used due to its low–computational complexity and better method for compressing the images. However it is suffered from the drawback of occupying high memory space and hence produced less throughput. This drawback is overcome in this work by adopting modified SPIHT algorithm termed as block-based pass-parallel SPIHT (BPS) algorithm. The designed architecture is compared with multi-precision floating point arithmetic units and the synthesis results are presented. From the experimental synthesis results it is proved that the integration of DWT structure integrated with log based FPU core and BPS coder implemented on FPGA devices provided efficient area and high speed of computations. The proposed architecture is designed using Verilog HDL and synthesized on various Xilinx FPGA devices. The architecture designed in this work is useful for compressing the images with good compression ratio, better resolution of images and to obtain high peak to signal ratio.

10.22161/ijaers/3.9.29