Implementation of Dynamic Frequency Controlled Parallel-Pixel Processing System

T. Roja latha, A.Anitha

Dynamic Frequency Control (DFC), Field Programmable Gate Array (FPGA), Parallel-Pixel Processing Architecture based on look-up-tabels(LUTs).

The main objective of this work is to develop an effective hardware system that respond to a run-time power constraint. These are handled on FPGAs by Dynamic Frequency Control (DFC) for the management of digital image and video processing architectures. In proposed design, the DFC is handled by utilising minimum resources. The pixel-processor architecture designed here is based on the implementation of single-pixel gamma correction operation. Here, the power and performance in-terms of throughput are constraints of digital image depend on the frequency of operations and number of pixel processing cores. The dynamic frequency controlled parallel-pixel processor is implemented on Virtex-6 FPGA’s and parallel-pixel processor architecture is verified by using System Generator.

10.22161/ijaers/3.9.6