Low Power and Low Voltage Double Tail Dynamic Latch Comparator using 180nm Technology

Balayan Sapna, Gupta Anshu

Double-tail comparator, dynamic clocked comparator, high-speed analog-to-digital converters (ADCs), low-power analog design.

The requirement for highly integrated and programmable analog-to-digital converters (ADCs), area efficiency, and ultra-low-power and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to amplify speed and power efficiency. In this paper, analytical expressions are derived and an analysis on the delay of the dynamic comparators will be presented. From the analytical expressions, designers can obtain an instinct about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the analysis made, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for fast operation and low-power even in small supply voltages. By adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in an 180nm CMOS technology confirm the analysis results.

10.22161/ijaers.4.4.17