Low Power Explicit Pulse Triggered Flip-Flop Design Based On A Pass Transistor

Amruta S. Vibhandik, Prof. P. V. Baviskar, Prof. K.N. Pawar

Flip-Flop, low power consumption, pulse triggered, high-speed.

In VLSI system design, power consumption is the ambitious issue for the past respective years. Advanced IC fabrication technology grants the use of nano scaled devices, so the power dissipation becomes major problem in the designing of VLSI chips. In this paper we present, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme using pass transistor. The offered design successfully figure out the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better power performance by consuming low power. The proposed design also significantly reduces delay time, set-up time and hold time. Simulation results based on TMC 180nm CMOS technology reveal that the proposed design features the best power and delay performance in several FF designs under comparison.

10.22161/ijaers/3.11.32