Ultra High MULTI CLOCK FREQUENCY BAUD RATE 128 Bit Multichannel PRBS CODEC ASIC I.P Core Design for High speed wireless internet Wi-Fi Routers, MODEM's, NIC's

Prof P.N.V.M Sastry, Prof.Dr.D.N.Rao, Dr.S.Vathsal

HDL - Hardware Description Language , MODEM - Modulator Demodulator, CODEC - Coding Decoding, Wi-Fi - Wireless internet Fidelity, I.T.U - International Telecom Unit, C.C.I.T.T - Consulting Committee for International Telegraph and Telephone , PRBS - Pseudo Random Binary Sequence ,FPGA - Field Programmable Gate Array.

The main aim is for HDL Design and Implementation of 128 Bit Multichannel PRBS CODEC for High Speed wireless internet computing products like Wi-Fi Routers, MODEM’s. this is very suit for very high speed internet computing products / applications of Big Parallel Network Data MODEM Interface based Computing Servers/Stations. This design consists of PRBS Encoder and Decoder Design of Different Channel Frequencies in terms of different PRBS Patterns Sequences – 2e7-1,2e10-1, 2e15-1, 2e23-1, 2e31-1, 2e48-1, 2e52-1, 2e64-1,2e128-1 by tapping through different feedback elements. Tapping of PRBS Done as per C.C.I.T.T – I.T.U O.150,O.151,O.152,O.153 Standards . these pattern sequences are encoded and decoded through different PRBS channel type selector/de-selector and outputs are generated through serial and parallel form of different PRBS Patterns. Programming design description done by Verilog HDL/VHDL and Design Synthesis & Implementation done through Xilinx ISE Software and Debugging done by Advanced FPGA Development Boards/Kits. Design Verification done through highly proficient Test Bench/Stimulus Design Module Codes.

10.22161/ijaers/3.9.20